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PEDS82V32520-01
1 Semiconductor MS82V32520
524,288-Word x 32-Bit x 2-Bank FIFO-SGRAM
This version:
Jul. 2001
Preliminary
GENERAL DESCRIPTION
The MS82V32520 is a 32-Mbit system clock synchronous dynamic random access memory. In addition to the conventional random read/write access function, the MS82V32520 provides the automatic row address increment function and automatic bank switching function. Therefore, if once the row and column addresses are set, continuous serial accesses are possible while banks are automatically switched till input of the Precharge command. The MS82V32520 is ideal for digital camera and TV buffer memory applications.
FEATURES
* * * * * * * * * * 524,288 words x 32 bits x 2 banks memory (2,048 rows x 256 columns x 32 bits x 2 banks) Single 3.3 V 0.3 V power supply LVTTL compatible inputs and outputs Programmable burst length (1, 2, 4, 8 and full page) Programmable CAS latency (2, 3) Automatic row address increment function and automatic bank switching function Power Down operation and Clock Suspend operation 4,096 refresh cycles/64 ms Auto refresh and self refresh capability Package: 86-pin 400 mil plastic TSOP (II) (TSOP (2) 86-P-400-0.50-K) (Product : MS82V32520-xxTA) xx indicates speed rank.
PRODUCT FAMILY
Family MS82V32520-75 MS82V32520-8 MS82V32520-10 Max. Operating Frequency 133 MHz 125 MHz 100 MHz Access Time 5.5 ns 6 ns 7 ns 86-pin Plastic TSOP (II) (400 mil) Package
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PIN CONFIGURATION (TOP VIEW)
VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 NC VCC DQM0 WE CAS RAS CS NC BA(A11) NC A10/AP A0 A1 A2 DQM2 VCC NC DQ16 VSSQ DQ17 DQ18 VCCQ DQ19 DQ20 VSSQ DQ21 DQ22 VCCQ DQ23 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VCCQ DQ30 DQ29 VSSQ DQ28 DQ27 VCCQ DQ26 DQ25 VSSQ DQ24 VSS
86-Pin Plastic TSOP (II) (Type K)
Pin Name A0 - A10 A0 - A7 BA(A11) CLK CKE CS RAS CAS Function Row Address Inputs Column Address Inputs Bank Address System Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Pin Name WE DQM0 - DQM3 DQ0 - DQ31 VCC VSS VCCQ VSSQ NC Function Write Enable DQ Mask Enable Data Inputs/outputs Supply Voltage Ground Supply Voltage for DQ Ground for DQ No Connection
Note: The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. For the four-bank 64Mb SDRAM, Pin 22 = BA0 and Pin 23 = BA1, and for the two-bank 64Mb SDRAM, Pin 22 = BA. Therefore, when the MS82V32520 is used in place of a 64Mb SDRAM, care must be taken in bank address control.
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BLOCK DIAGRAM
CKE CLK CS RAS CAS WE DQM0 to DQM3
I/O Controller
Timing Register
Bank
BA
Controller
Internal Col. Address
A0 to A10 BA
Counter
Input Data Register Input Buffers
Column
32
32
88 Address
Buffers
Column Decoders Sense Amplifiers
32
Read Data Register
32
Output Buffers
32
DQ0 to DQ31
Internal Row Address Counter
Row Decoders Row
Word Drivers Word Drivers
16Mb Memory Cells Bank A 16Mb Memory Cells Bank B
Row
Decoders
11
Address Buffers
Sense Amplifiers
8
Column Decoders
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PIN DESCRIPTION
CLK CS CKE Fetches all inputs at the "H" edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQM0, DQM1, DQM2 and DQM3. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Row & column multiplexed. Row address: RA0 - RA10 Column address: CA0 - CA7 Selects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. BA = "L": Bank A BA = "H": Bank B Functionality depends on the combination. For details, see the function truth table. Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and DQM3 controls DQ24 to DQ31. Data inputs/outputs are multiplexed on the same pin.
Address
BA RAS CAS WE
DQM0 - DQM3
DQ0 - DQ31
*Notes: 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, DQM0, DQM1, DQM2, and DQM3 are invalid. 2. When issuing an active, read or write command, the bank is selected by BA.
BA 0 1 Active, read or write Bank A Bank B
3. The auto precharge function is enabled or disabled by the A10/AP input when the read or write command is issued.
A10/AP 0 1 0 1 BA 0 0 1 1 Operation After the end of burst, bank A holds the active status. After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the active status. After the end of burst, bank B is precharged automatically.
4. When issuing a precharge command, the bank to be precharged is selected by the A10/AP and BA inputs.
A10/AP 0 0 1 BA 0 1 x Operation Bank A is precharged. Bank B is precharged. Both banks A and B are precharged.
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COMMAND OPERATION
Mode Register Set Command (CS RAS CAS WE = "Low") CS, CS RAS, CAS, The MS82V32520 has the mode register that defines the operation mode "CAS Latency, Burst Length, Burst Sequence". The Mode Register Set command should be executed just after the MS82V32520 is powered on. Before entering this command, all banks must be precharged. Next command can be issued after tRSC. Auto Refresh Command (CS RAS CAS = "Low", WE = "High") CS, CS RAS, The Auto Refresh command performs refresh automatically by the address counter. The refresh operation must be performed 4,096 times within 64 ms and the next command can be issued after tRC from last Auto Refresh command. Before entering this command, all banks must be precharged. Self Refresh Entry/Exit Command (CS RAS CAS CKE = "Low", WE = "High") CS, CS RAS, CAS, The self refresh operation continues after the Self Refresh Entry command is entered, with CKE level left "low". This operation terminates by making CKE level "high". The self refresh operation is performed automatically by the internal address counter on the MS82V32520 chip. In self refresh mode, no external refresh control is required. Before entering self refresh mode, all banks must be precharged. Next command can be issued after tRC. Single Bank Precharge Command (CS RAS WE A10/AP = "Low", CAS = "High") CS, CS RAS, WE, The Single Bank Precharge command triggers bank precharge operation. Precharge bank is selected by BA. All Banks Precharge Command (CS RAS WE = "Low", CAS A10/AP = "High") CS, CAS, CS RAS, The All Bank Precharge command triggers precharge of both of the banks A and B. If this command is executed during special bank active mode, the special bank active mode is terminated. Bank Active Command (CS RAS = "Low", CAS WE = "High") CS, CAS, CS The Bank Active command activates the bank selected by BA. The Bank Active command corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 - A10 and BA" are strobed. Write Command (CS CAS WE A10/AP = "Low", RAS = "High") CS, CS CAS, WE, The Write command is required to begin burst write operation. Then burst access initial bit column address is strobed. Write with Auto Precharge Command (CS CAS WE = "Low", RAS A10/AP = "High") CS, RAS, CS CAS, The Write with Auto Precharge command is required to begin burst write operation with automatic precharge after the burst write. Any command that interrupts this operation cannot be issued. Read Command (CS CAS A10/AP = "Low", RAS WE = "High") CS, RAS, CS CAS, The Read command is required to begin burst read operation. Then burst access initial bit column address is strobed.
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Read with Auto Prechaege Command (CS CAS = "Low", RAS WE A10/AP = "High") CS, RAS, WE, CS The Read with Auto Precharge command is required to begin burst read operation with auto precharge after the burst read. Any command that interrupts this operation cannot be issued. No Operation Command (CS = "Low", RAS CAS WE = "High") RAS, CAS, CS The No Operation command does not trigger any operation. Device Deselect Command (CS = "High") CS The Device Deselect command disables the RAS, CAS, WE and Address input. This command does not trigger any operation. Data Write/Output Enable Command (DQMi = "Low") The Data Write/Output Enable command enables DQ0 - DQ31 in read or write. The each DQM0, 1, 2 and 3 corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24 - DQ31 respectively. Data Mask/Output Disable Command (DQMi = "High") The Data Mask/Output Disable command disables DQ0 - DQ31 in read or write. In read cycle output buffers are disabled after 2 clocks . In write cycle input buffers are disabled at the same clock. The each DQM0, 1, 2 and 3 corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24 - DQ31 respectively. Burst Stop Command (CS WE = "Low", RAS CAS = "High") CS, RAS, CS The Burst Stop command stops burst access. After the Burst Stop command is entered, the output buffer goes into high impedance state.
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SPECIAL READ/WRITE OPERATION
The special read or write operation is activated by executing the Read or Write command after selecting the special page mode with the Mode Register command. The automatic bank switching and automatic row address increment operations are activated by executing the Bank Active command during Special Page mode, and the serial access starts from the address fetched with the Read or Write command. The burst operation starts from the start address toward the column. When the last column address is reached, the bank is automatically switched and the row address is also automatically incremented and the serial access continues from the start column address. The automatic bank switching and automatic row address increment operations continue until the All Bank Precharge command is executed each time the last column address is reached. Since the bank switching and row address increment are automatically made during the special read or write operation, the row address proceeds as shown in the following figure. (1) When a select row address is n (n<2048), nn + 2048n + 1n + 1 + 2048n + 2n + 2 + 2048*** (2) When a select row address is m (m>2047), mm + 1 - 2048m + 1m + 2 - 2048m + 2m + 3 - 2048***
Bank-A 0 2047 2048 Bank-B 4095 256 Operation is ended by input of All Bank Precharge command Start Address
Column 0 Row Select orders of row address
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TRUTH TABLE
Command Truth Table
Function Device Deselect No Operation Mode Register Set Auto Refresh Bank Activate Read Read with Auto Precharge Write Write with Auto Precharge Precharge Select Bank Precharge All Banks Burst Stop CS H L L L L L L L L L L L RAS x H L L L H H H H L L H CAS x H L L H L L L L H H H WE x H L H H H H L L L L L x BA BA BA BA BA BA x x L H L H L H x Address BA x x A10/AP x x OP. CODE x RA CA (A7 - A0) CA (A7 - A0) CA (A7 - A0) CA (A7 - A0) x x x x A9 - A0 x x
DQM Truth Table
Function Data Write/Output Enable Data Mask/Output Disable DQMi L H
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Function Truth Table (1/3)
Note 1 Current State Idle CS H L L L L L L L Active (ACT) H L L L L L L Active (Special Page Mode) (SACT) H L L L L L L L Read (RD) H L L L L L L L Write (WT) H L L L L L L L RAS x H H H L L L L x H H H L L L x H H H L L L L x H H H H L L L x H H H H L L L CAS x H H L H L H L x H L L H H L x H L L H H H L x H H L L H H L x H H L L H H L WE x H L x H L L H x x H L H L x x x H L H L L x x H L H L H L x x H L H L H L x BA x x BA BA BA L BA x x x BA BA BA BA x x x BA BA BA BA BA x x x x BA BA BA BA x x x x BA BA BA BA x Address x x x CA, A10 RA A10 x x x CA, A10 CA, A10 RA A10 x x x CA CA RA A10: L A10: H x x x x CA, A10 CA, A10 RA A10 x x x x CA, A10 CA, A10 RA A10 x NOP NOP ILLEGAL ILLEGAL Row Active NOP Auto Refresh/Self refresh NOP NOP Read Write ILLEGAL Precharge ILLEGAL NOP NOP Serial Read Serial Write ILLEGAL ILLEGAL Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Burst Stop Row Active Term Burst, new Read Term Burst, start Write ILLEGAL Term Burst, execute Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Burst Stop Row Active Term Burst, start Read Term Burst, new Write ILLEGAL Term Burst, execute Precharge ILLEGAL 3 3 2 3 3 3 2 2 4 5 2 2 Action Note
Op-Code Mode Register Write
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Function Truth Table (2/3)
Note 1 Current State Read with Auto Precharge (RAP) CS H L L L L L L L Write with Auto Precharge (WAP) H L L L L L L L Read (Special Page Mode) (SRD) H L L L L L L L Write (Special Page Mode) (SWT) H L L L L L L L Precharging (PRE) H L L L L L L RAS x H H H H L L L x H H H H L L L x H H H L L L L x H H H L L L L x H H H L L L CAS x H H L L H H L x H H L L H H L x H H L H H H L x H H L H H H L x H H L H H L WE x H L H L H L x x H L H L H L x x H L x H L L x x H L x H L L x x H L x H L x BA x x x BA BA BA BA x x x x BA BA BA BA x x x x BA BA BA BA x x x x BA BA BA BA x x x BA BA BA BA x Address x x x CA, A10 CA, A10 RA A10 x x x x CA, A10 CA, A10 RA A10 x x x x CA RA A10: L A10: H x x x x CA RA A10: L A10: H x x x x CA RA A10 x Action NOP (Continue Burst to End and enter Precharge) NOP (Continue Burst to End and enter Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to End and enter Precharge) NOP (Continue Burst to End and enter Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Continue serial read) NOP (Continue serial read) ILLEGAL ILLEGAL ILLEGAL ILLEGAL Precharging ILLEGAL NOP (Continue serial write) NOP (Continue serial write) ILLEGAL ILLEGAL ILLEGAL ILLEGAL Precharging ILLEGAL NOP Idle after tRP NOP Idle after tRP ILLEGAL ILLEGAL ILLEGAL NOP ILLEGAL 2 2 2 4 2 2 2 2 Note
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Function Truth Table (3/3)
Note 1 Current State Refreshing (REF) CS H L L L L L L RAS x H H H L L L CAS x H H L H H L WE x H L x H L x BA x x BA BA BA BA x Address x x x CA RA A10 x Action NOP Idle after tRC NOP Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Note
ABBREVIATIONS BA = Bank Address NOP = No Operation command
RA = Row Address
CA = Column Address
Notes: 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. To avoid bus contention, satisfy tCCD and tDPL. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10/AP. 5. Illegal if any bank is not idle.
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Function Truth Table for CKE
Current State (n) Self Refresh (SREF) CKEn-1 CKEn H L L L L L L Power Down (PD) H L L L L L L All Banks Idle (ABI) H H H H H H H H L Any State Other than Listed Above H H L L x H H H H H L x H H H H H L H L L L L L L L L H L H L CS x H L L L L x x H L L L L x x H L L L L L L x x x x x RAS x x H H H L x x x H H H L x x x H H H L L L x x x x x CAS x x H H L x x x x H H L x x x x H H L H L L x x x x x WE x x H L x x x x x H L x x x x x H L x L H L x x x x x Address x x x x x x x x x x x x x x x x x x x x x x x x x x x INVALID Exit Self Refresh ABI Exit Self Refresh ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Self Refresh ABI Exit Self Refresh ABI ILLEGAL ILLEGAL ILLEGAL NOP (Continue power down mode) Refer to Truth Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Truth Table Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension 6 6 6 6 6 6 6 6 6 Action Note
Note:
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
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Mode Set Address Keys
Operation Code A8 A7 0 0 1 1 A9 0 1 0 1 0 1 TM Mode Setting Vender Use Only
*Note 1
CAS Latency A6 A5 A4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CL Reserved Reserved 2 3 Reserved Reserved Reserved Reserved 0 1
Burst Type A3 BT Sequential Interleave A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Burst Length BT = 0 1 2 4 8 Reserved Reserved Special page Full Page BT = 1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved
Write Burst Length Length Burst Single Bit
*Note 1: To select Special Page mode, set A9 to "L". The write burst length during Special Page mode is set only for Burst. POWER ON SEQUENCE 1. With CKE = "H", DQM = "H" and the other inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 s or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply an Auto-refresh 8 or more times. 5. Enter the mode register command.
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Burst Length and Sequence BL = 2
Starting Address (column address A0, binary) 0 1 Sequential Type 0, 1 1, 0 Interleave Type Not supported Not supported
BL = 4
Starting Address (column address A1, A0, binary) 00 01 10 11 Sequential Type 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Interleave Type 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
BL = 8
Starting Address (column address A2 - A0, binary) 000 001 010 011 100 101 110 111 Sequential Type 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave Type 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
BL = Special, Full : Sequential only
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READ/WRITE COMMAND INTERVAL
Read to Read Command Interval
BL = 4, CL = 2 0 CLK RD-A RD-B DQ 1cycle QA1 QB1 QB2 QB3 QB4 Hi-Z 1 2 3 4 5 6 7 8
Write to Write Command Interval
BL = 4, CL = 2 0 CLK WT-A WT-B DQ DA1 DB1 DB2 DB3 DB4 Hi-Z 1 2 3 4 5 6 7 8
1cycle
Write to Read Command Interval
BL = 4 0 CLK CL = 2 DQ CL = 3 DQ WT-A RD-B DA1 Hi-Z QB1 QB2 QB3 QB4 1 2 3 4 5 6 7 8
WT-A RD-B DA1 1cycle Hi-Z QB1 QB2 QB3 QB4
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Read to Write Command Interval
BL = 4, CL = 2, 3 0 CLK CL = 2, 3 DQM DQ Hi-Z DB1 1cycle DB2 DB3 DB4 RD-A WT-B 1 2 3 4 5 6 7 8
BL = 4, CL = 2, 3 0 CLK CL = 2 DQM DQ Hi-Z QA1 QA2 QA3 DB1 DB2 Hi-Z is necessary WT-B RD-A WT-B 1 2 3 4 5 6 7 8
CL = 3 DQM DQ
RD-A
Hi-Z
QA1
QA2
DB1 Hi-Z is necessary
DB2
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BURST TERMINATION
Burst Read Termination by Precharging in READ Cycle
BL = 2, 4, 8, Full 0 CLK CL = 2 DQ CL = 3 DQ RD Q1 RD Q1 Q2 PRE Q3 PRE Q2 Q3 Q4 Q4 tRP ACT Hi-Z 1 2 3 4 5 tRP ACT Hi-Z 6 7 8
Burst Read Termination by Precharging in WRITE Cycle
BL = 2, 4, 8, Full 0 CLK CL = 2 DQ CL = 3 DQ WT D1 WT D1 D2 D3 D4 D2 D3 D4 PRE D5 PRE D5 Hi-Z 1 2 3 4 5 tRP ACT Hi-Z tRP ACT 6 7 8
Note: D5 data will not be written
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Read Burst Stop Command
BL = 2, 4, 8, Full 0 CLK RD CL = 2 DQ CL = 3 DQ Q1 Q2 Q1 BST Q3 Q2 Q4 Q3 Hi-Z Hi-Z 1 2 3 4 5 6 7 8
Q4
Write Burst Stop Command
BL = 2, 4, 8, Full 0 CLK WT CL = 2, 3 DQ D1 D2 D3 D4 BST Hi-Z 1 2 3 4 5 6 7 8
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AUTO PRECHARGE
Read with Auto Precharge
BL = 4 0 CLK CL = 2 DQ CL = 3 DQ RAP RAP Q1 Auto precharge starts Q2 Q3 Q4 Hi-Z 1 2 3 4 5 6 7 8
Auto precharge starts Q1 Q2 Q3 Q4 Hi-Z
(tRAS is satisfied)
Write with Auto Precharge
BL = 4 0 CLK CL = 2 DQ CL = 3 DQ WAP D1 WAP D1 D2 D3 D2 D3 Auto precharge starts D4 Auto precharge starts D4 Hi-Z (tRAS is satisfied) Hi-Z 1 2 3 4 5 6 7 8
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Power Supply Pin Relative to GND Voltage on Input Pin Relative to GND Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VCC VIN, VOUT IOS PD* Topr Tstg Rating -0.5 to 4.6 -0.5 to VCC + 0.5 4.6 50 1 0 to 70 -55 to 150 Unit V V mA W C C
*: Ta = 25 C Recommended Operating Conditions
(Ta = 0 to 70C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 3.0 0 2.0 -0.3 Typ. 3.3 0 -- -- Max. 3.6 0 VCC + 0.3 0.8 Unit V V V V
Capacitance
(VCC = 3.3 V 0.3 V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (A0 - A10, BA) Input Capacitance (CLK, CKE, CS, RAS, CAS, WE DQM 0 - DQM3) Output Capacitance (DQ0 - DQ31) Symbol CIN1 CIN2 COUT Min. -- -- -- Max. 5 5 6 Unit pF pF pF
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DC Characteristics
Parameter Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Operating Current (1 Bank) Precharge Standby Current in Power Down Mode Symbol VOH VOL ILI ILO ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 ICC5 ICC6 Test Condition CKE -- -- -- -- Other IOL= 2.0 mA -- --
MS82V32520-75 MS82V32520-8 MS82V32520-10
Min. Max. Min. Max. Min. Max. -- 0.4 10 10 200 2 2 40 20 3 3 50 30 240 200 3 2.4 -- -10 -10 -- -- -- -- -- -- -- -- -- -- -- -- -- 0.4 10 10 190 2 2 40 20 3 3 50 30 220 190 3 2.4 -- -10 -10 -- -- -- -- -- -- -- -- -- -- -- -- -- 0.4 10 10 180 2 2 40 20 3 3 50 30 200 180 3 -- -10 -10 -- -- -- -- -- -- -- -- -- -- -- --
Unit Note V V A A mA mA mA mA mA mA mA mA mA mA mA mA 3 3 3 3 2 1, 2 3 2 2
IOH= -2.0 mA 2.4
tCK = tCK min. CKE VIH tRC = tRC min. No Burst CKE VIL tCK = tCK min. CKE VIL CKE VIH CKE VIH CLK VIL tCK = CS VIH tCK = tCK min. CLK VIL tCK = CLK VIL tCK = CS VIH tCK = tCK min. CLK VIL tCK =
Precharge Standby Current in Non Power Down Mode
Active Standby Current in Power Down Mode
CKE VIL tCK = tCK min. CKE VIL CKE VIH CKE VIH
Active Standby Current in Non Power Down Mode Operating Current (Burst Mode) Refresh Current Self Refresh Current
CKE VIH tCK = tCK min. CKE VIH tRC tRC min. CKE 0.2V --
Notes 1. The maximum value of power supply current is obtained with the output open. 2. Address and data are changed only one time during one cycle. 3. Address and data are changed only one time during two cycles.
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AC Characteristics Test conditions * AC measurements assume tT = 1 ns. * Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. * If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX). * An access time is measured at 1.4 V. * Input levels at the AC testing are 2.4 V/0.4 V.
tCK 2.4 V CLK 1.4 V 0.4 V 2.4 V Input 1.4 V 0.4 V tOH Output 1.4 V 1.4 V tCH tCL
tSetup tHold tAC
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MS82V32520
Synchronous Characteristics
Parameter Clock Cycle Time Access Time from CLK CLK High Level Width CLK Low Level Width Data-out Hold Time Data-out Low-impedance Time Data-out High-impedance Time Data-in Setup Time Data-in Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command (CS, RAS, CAS, WE, DQM) Setup Time Command (CS, RAS, CAS, WE, DQM) Hold Time CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 Symbol tCK3 tCK2 tAC3 tAC2 tCH tCL tOH tLZ tHZ tDS tDH tAS tAH tCKS tCKH tCMS tCMH MS82V32520-75 MS82V32520-8 MS82V32520-10 Min. 7.5 12 -- -- 3 3 2.5 0 -- 2.5 1 2.5 1 2.5 1 2.5 1 Max. -- -- 5.5 8 -- -- -- -- 5.5 -- -- -- -- -- -- -- -- Min. 8 12 -- -- 3 3 2.5 0 -- 2.5 1 2.5 1 2.5 1 2.5 1 Max. -- -- 6 8 -- -- -- -- 6 -- -- -- -- -- -- -- -- Min. 10 15 -- -- 3.5 3.5 2.5 0 -- 2.5 1 2.5 1 2.5 1 2.5 1 Max. -- -- 7 9 -- -- -- -- 7 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 Note
Note 1. Output load.
1.4 V Z = 50 Output 50 pF 50
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MS82V32520
Asynchronous Characteristics
Parameter REF to REF/ACT/SACT Command Period ACT to PRE Command Period SACT to PRE Command Period PRE to ACT Command Period PRE-ALL (Special Page) to SACT Command Period Delay Time ACT/SACT to READ/WRITE Command ACT (0) to ACT (1) Command Period READ/WRITE to READ/WRITE Command Period Data-in to PRE Command Period Data Output to WRITE Command Input Time Mode Register Set Cycle Time Transition Time Refresh Time Symbol tRC tRAS tRASS tRP tRPS tRCD tRRD tCCD tDPL tOWD tRSC tT tREF MS82V32520-75 MS82V32520-8 MS82V32520-10 Min. 67.5 45 6 22.5 9 22.5 15 7.5 7.5 15 15 1 -- Max. -- 120k -- -- -- -- -- -- -- -- -- 30 64 Min. 72 48 6 24 9 24 16 8 8 16 16 1 -- Max. -- 120k -- -- -- -- -- -- -- -- -- 30 64 Min. 90 60 6 30 9 30 20 10 10 20 20 1 -- Max. -- 120k -- -- -- -- -- -- -- -- -- 30 64 Unit ns ns CLK ns CLK ns ns ns ns ns ns ns ms Note
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MS82V32520
TIMING WAVEFORM
READ/WRITE CYCLE (BL = 2, CL = 3)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ Hi-Z
tRCD RAa RAa CAa tCMS CAb tCMH tAC tOH tLZ tHZ tDS tDH
DAb1 DAb2
tCK
1
2
tCL
3
4
5
6
7
8
9
10 11
12
13
14
15
16
tCKH
17
18
19
tCKS tCH
tCMS tCMH
tAS tAH
RBa RBa
QAa1 QAa2
tOWD tRAS
tDPL tRP
tRC WT-A PRE-A
ACT-A
RD-A
ACT-B
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MS82V32520
Special READ CYCLE (BL = Special Page, CL = 3)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L Hi-Z tRCD
QAa1 QAa2 QAa3 QAa4 Qn-1
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
H
RAa RAa CAa
RBa RBa
Qn Qn+1 Qn+2
tRASS SRD-A Special Read Start PRE-ALL
tRPS SACT-B
SACT-A
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MS82V32520
Special WRITE CYCLE (BL = Special Page, CL = 3)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L Hi-Z H
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
RAa RAa CAa
RBa RBa
tRCD
DAa1 DAa2 DAa3 DAa4 DAa5
Dn-2 Dn-1 Dn
tRASS SWT-A Special Write Start
tDPL
tRPS SACT-B
SACT-A
PRE-ALL
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MS82V32520
Mode Register Set
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ Hi-Z H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
PRE-ALL
tRP
MRA
tRSC
ACT
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MS82V32520
Auto Reflesh
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L Hi-Z H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
PRE-ALL tRP
REF tRC
REF tRC
ACT
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MS82V32520
Self Reflesh (Entry and Exit)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L Hi-Z H
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
PRE-ALL tRP
SELF Entry
SELF Exit
tRC
SELF Entry
SELF Exit
ACT tRC
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MS82V32520
Burst Termination by Precharging (BL = 8, CL = 3)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L Hi-Z
DAa1 DAa2 QAb1 QAb2 QAb3 QAb4
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
H
RAa RAa CAa
RAb RAb CAb
ACT-A
WT-A
PRE-A
ACT-A
RD-A
PRE-A PRE Command Termination
PRE Command Termination
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MS82V32520
Auto Precharging (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L Hi-Z
QAa1 QAa2 QAa3 QAa4 DBa1 DBa2 DBa3 DBa4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
H
RAa RAa
RBa CAa RBa CBa
ACT-A
RAP-A
ACT-B AP-A
WAP-B AP-B
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MS82V32520
Power Down Mode and Clock Suspension (BL = 4, CL = 2)
0 CLK tCKS CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L Hi-Z
QAa1 QAa2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa RAa CAa
QAa3
QAa4
ACT-A PD Entry
RD-A PD Exit Clock Mask Start Clock Mask End
PRE-A PD Entry PD Exit
ACTIVE STANDBY
PRECHARGE STANDBY
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MS82V32520
CLOCK Suspend Exit & Power Down Exit
1) Clock Suspend (= Active Power Down) Exit 2) Power Down (= Precharge Power Down) Exit
CLK CKE Internal CLK Command
Note 1
CLK
Note 3
tCKS
CKE Internal CLK RD Command
Note 2
tCKS
NOP ACT
Notes: 1. Active power down: one or both bank active state. 2. Precharge power down: both bank precharge state. 3. NOP should be issued. And new command can be issued after 1 Clock.
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MS82V32520
Byte Read/Write Operation (by DQM) (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM0 DQM1 DQ 0-7 DQ 8 - 15
QBa1 QBa2 QBa3 DBb2 DBb3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
H
RBa RBa CBa CBb
QBa2 QBa3 QBa4
DBb1 DBb2
DBb4
ACT-B
RD-B Byte of DQ8-15 not Read
WT-B Byte of Byte of Byte of Byte of DQ0-7 DQ0-7 DQ8-15 DQ0-7 not Read not Write not Write not Write
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MS82V32520
Burst Read and Single Write (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L Hi-Z
QAa1 QAa2 QAa3 QAa4
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
H
RAa RAa CAa CBb CBb
DBb
DBc
ACT-B
RD-B
Single WT
Single WT
PRE-B
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MS82V32520
Random Column Read (Continuous Read of Same Bank) (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa RAa CAa CAb CAc
RAi RAi
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
ACT-A
RD-A
RD-A
RD-A
PRE-A
ACT-A
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MS82V32520
Random Column Write (Continuous Write of Same Bank) (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RBa RBa CBa CBb CBc
RBi RBi
DBa1 DBa2 DBa3 DBa4 DBb1 DBb2 DBc1 DBc2 DBc3 DBc4
ACT-B
WT-B
WT-B
WT-B
PRE-B
ACT-B
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MS82V32520
Interleaved Column Read (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L H
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
RAa RAa
RBa CAa RBa CBa CBb CAb
QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBb1 QBc2 QAb1 QAb2 QAb3 QAb4
ACT-A
RD-A ACT-B tRCD tRRD
RD-B
RD-B
RD-A
PRE-B
PRE-A
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MS82V32520
Interleaved Column Write (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A10 /AP ADD DQM 0-3 DQ L H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa RAa
RBa CAa RBa CBa CBb CAb
DAa1 DAa2 DAa3 DAa4 DBa1 DBa2 DBb1 DBb2 DAb1 DAb2 DAb3 DAb4
ACT-A
WT-A ACT-B tRCD tRRD
WT-B
WT-B
WT-A
PRE-B
PRE-A
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MS82V32520
PACKAGE DIMENSIONS
(Unit: mm)
TSOP(2)86-P-400-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.53 TYP. 1/Jul. 14, 1998
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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MS82V32520
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd.
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